In base stations of mobile communication, terrestrial digital broadcasting, and the like, a frequency reference signal is required to have high frequency stability. A standard signal is obtained from a cesium frequency standard oscillator, a rubidium standard oscillator, and the like, but since the standard signal thereof generally costs high, each of the base stations distributes the standard signal when using it. The distributed standard signal is used, for example, as a reference signal for phase comparison of a PLL circuit, and from this PLL circuit, a reference signal such as, for example, a reference clock signal with a required frequency can be obtained.
As shown in FIG. 14, generally, in a PLL circuit, a phase comparator 104 compares a standard signal 101 and a signal that a frequency divider circuit 103 obtains by frequency-dividing an output signal of a voltage-controlled oscillator 102, and a charge pump 105 gives a signal according to a phase difference between these signals and supplies its output to the voltage-controlled oscillator 102 via a loop filter 106, whereby the PLL circuit performs PLL control to generate a high-accuracy signal (patent document 1).
There has been an increasing demand for higher accuracy of a frequency reference signal in, for example, a base station. For example, the present inventor has been trying to develop a frequency synthesizer having frequency resolution in a 1 Hz unit or lower, but a reference clock signal in such an apparatus needs to have extremely high frequency stability, and a conventional PLL circuit has difficulty in satisfying this requirement.
Patent document 1
Japanese Patent Application Laid-open No. 2001-326573